
// Library name: VLSI_PROJECT
// Cell name: amk_inverter
// View name: schematic
subckt amk_inverter VDD VSS in out
    T1 (out in VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (out in VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 nrs=1.5652 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_inverter
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_buf
// View name: schematic
subckt amk_buf VDD VSS bout in
    I1 (VDD VSS net10 bout) amk_inverter
    I0 (VDD VSS in net10) amk_inverter
ends amk_buf
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: buf_string
// View name: schematic
subckt buf_string VDD VSS in out
    I14 (VDD VSS out net10) amk_buf
    I13 (VDD VSS net10 net14) amk_buf
    I12 (VDD VSS net14 net18) amk_buf
    I11 (VDD VSS net18 net22) amk_buf
    I10 (VDD VSS net22 net42) amk_buf
    I9 (VDD VSS net26 net46) amk_buf
    I8 (VDD VSS net30 net26) amk_buf
    I7 (VDD VSS net34 net30) amk_buf
    I6 (VDD VSS net38 net34) amk_buf
    I5 (VDD VSS net42 net38) amk_buf
    I4 (VDD VSS net46 net50) amk_buf
    I3 (VDD VSS net50 net54) amk_buf
    I2 (VDD VSS net54 net58) amk_buf
    I1 (VDD VSS net58 net62) amk_buf
    I0 (VDD VSS net62 in) amk_buf
ends buf_string
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_nand_3in
// View name: schematic
subckt amk_nand_3in VDD VSS a b c z
    T4 (net10 c VSS VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (z a net18 VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net18 b net10 VSS) lpnfet l=120.0n w=440.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.42e-13 as=2.42e-13 pd=1.98u ps=1.98u nrd=0.4091 nrs=0.4091 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (z c VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (z a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (z b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_nand_3in
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_nand
// View name: schematic
subckt amk_nand VDD VSS a b z
    T1 (z b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (z a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net17 b VSS VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (z a net17 VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_nand
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_latch_qb
// View name: schematic
subckt amk_latch_qb D Q QB VDD VSS clk clr
    I5 (VDD VSS Q net066 clr QB) amk_nand_3in
    I3 (VDD VSS clk net28 clr net066) amk_nand_3in
    I0 (VDD VSS D clk net9) amk_nand
    I2 (VDD VSS net9 QB Q) amk_nand
    I4 (VDD VSS D net28) amk_inverter
ends amk_latch_qb
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_dff_qb
// View name: schematic
subckt amk_dff_qb D Q QB VDD VSS clk clr
    I4 (D net9 net024 VDD VSS net19 net038) amk_latch_qb
    I1 (net9 Q QB VDD VSS clk net038) amk_latch_qb
    I6 (VDD clk clr net038) amk_inverter
    I2 (VDD VSS clk net19) amk_inverter
ends amk_dff_qb
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_3in_and
// View name: schematic
subckt amk_3in_and VDD VSS a b c z
    I0 (VDD VSS net17 z) amk_inverter
    T5 (net17 c VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net17 a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net17 b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T4 (net048 c VSS VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net21 b net048 VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 \
        ngcon=1 ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 \
        nrs=0.375 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p \
        panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p \
        sa=5.5e-07 sb=5.5e-07 sd=0u dtemp=0
    T0 (net17 a net21 VSS) lpnfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_3in_and
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_2in_and
// View name: schematic
subckt amk_2in_and VDD VSS a b z
    T0 (net17 a net13 VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net13 b VSS VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net17 a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net17 b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    I0 (VDD VSS net17 z) amk_inverter
ends amk_2in_and
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_dff_fe
// View name: schematic
subckt amk_dff_fe D Q VDD VSS clk rst
    I7 (D net028 net030 VDD VSS clk rstb) amk_latch_qb
    I8 (net028 Q net020 VDD VSS net7 rstb) amk_latch_qb
    I9 (VDD VSS rst rstb) amk_inverter
    I2 (VDD VSS clk net7) amk_inverter
ends amk_dff_fe
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_2in_or
// View name: schematic
subckt amk_2in_or VDD VSS a b z
    I0 (VDD VSS net21 z) amk_inverter
    T1 (net12 a VDD VDD) lppfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (net21 b net12 VDD) lppfet l=120.0n w=480.0n nf=1 m=1 par=1 ngcon=1 \
        ad=2.64e-13 as=2.64e-13 pd=2.06u ps=2.06u nrd=0.375 nrs=0.375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net21 a VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.125 nrs=1.125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (net21 b VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.125 nrs=1.125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_2in_or
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: sar_mux
// View name: schematic
subckt sar_mux VDD VSS in0 in1 out sel0
    I1 (VDD VSS net54 net49 out) amk_2in_or
    I0 (VDD VSS sel0 sel0b) amk_inverter
    I9 (VDD VSS in1 sel0 net49) amk_2in_and
    I6 (VDD VSS in0 sel0b net54) amk_2in_and
ends sar_mux
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: SAR_logic2
// View name: schematic
I126 (VDD VSS clock clk) buf_string
I63 (VDD beginProc net0168 VDD VSS clk9 reset) amk_dff_qb
I10 (VDD VSS c3 c3b) amk_inverter
I9 (VDD VSS c2 c2b) amk_inverter
I8 (VDD VSS c1 c1b) amk_inverter
I7 (VDD VSS c0 c0b) amk_inverter
I42 (VDD VSS c2_0 c2_1 clk clk2) amk_3in_and
I52 (VDD VSS c0_0 c0_1 clk clk0) amk_3in_and
I47 (VDD VSS c1_0 c1_1 clk clk1) amk_3in_and
I37 (VDD VSS c3_0 c3_1 clk clk3) amk_3in_and
I32 (VDD VSS c4_0 c4_1 clk clk4) amk_3in_and
I17 (VDD VSS c7_0 c7_1 clk clk7) amk_3in_and
I12 (VDD VSS c8_0 c8_1 clk clk8) amk_3in_and
I6 (VDD VSS c9_0 c9_1 clk clk9) amk_3in_and
I27 (VDD VSS c5_0 c5_1 clk clk5) amk_3in_and
I22 (VDD VSS c6_0 c6_1 clk clk6) amk_3in_and
I68 (VDD VSS clk7 beginProc net0263) amk_2in_and
I67 (VDD VSS clk8 beginProc net0268) amk_2in_and
I74 (VDD VSS clk1 beginProc net0264) amk_2in_and
I75 (VDD VSS clk0 beginProc net0259) amk_2in_and
I69 (VDD VSS clk6 beginProc net0203) amk_2in_and
I71 (VDD VSS clk4 beginProc net0279) amk_2in_and
I72 (VDD VSS clk3 beginProc net0274) amk_2in_and
I73 (VDD VSS clk2 beginProc net0269) amk_2in_and
I54 (VDD VSS c2b c3 c0_1) amk_2in_and
I53 (VDD VSS c0 c1b c0_0) amk_2in_and
I43 (VDD VSS c0 c1 c2_0) amk_2in_and
I44 (VDD VSS c2 c3b c2_1) amk_2in_and
I70 (VDD VSS clk5 beginProc net0199) amk_2in_and
I48 (VDD VSS c2b c3 c1_1) amk_2in_and
I49 (VDD VSS c0b c1b c1_0) amk_2in_and
I39 (VDD VSS c0b c1 c3_0) amk_2in_and
I38 (VDD VSS c2 c3b c3_1) amk_2in_and
I34 (VDD VSS c2 c3b c4_1) amk_2in_and
I33 (VDD VSS c0 c1b c4_0) amk_2in_and
I29 (VDD VSS c0b c1b c5_0) amk_2in_and
I28 (VDD VSS c2 c3b c5_1) amk_2in_and
I19 (VDD VSS c0b c1 c7_0) amk_2in_and
I18 (VDD VSS c2b c3b c7_1) amk_2in_and
I14 (VDD VSS c2b c3b c8_1) amk_2in_and
I13 (VDD VSS c0 c1b c8_0) amk_2in_and
I66 (VDD VSS clk9 beginProc net0215) amk_2in_and
I65 (VDD VSS c2b c3b c9_1) amk_2in_and
I3 (VDD VSS c0b c1b c9_0) amk_2in_and
I23 (VDD VSS c0 c1 c6_0) amk_2in_and
I24 (VDD VSS c2b c3b c6_1) amk_2in_and
I45 (net0310 bit2 VDD VSS net0269 reset) amk_dff_fe
I55 (net0371 bit0 VDD VSS net0259 reset) amk_dff_fe
I57 (VDD done VDD VSS net0259 reset) amk_dff_fe
I50 (net0377 bit1 VDD VSS net0264 reset) amk_dff_fe
I40 (net180 bit3 VDD VSS net0274 reset) amk_dff_fe
I35 (net186 bit4 VDD VSS net0279 reset) amk_dff_fe
I30 (net192 bit5 VDD VSS net0199 reset) amk_dff_fe
I20 (net204 bit7 VDD VSS net0263 reset) amk_dff_fe
I15 (net210 bit8 VDD VSS net0268 reset) amk_dff_fe
I2 (net216 bit9 VDD VSS net0215 reset) amk_dff_fe
I25 (net198 bit6 VDD VSS net0203 reset) amk_dff_fe
I81 (VDD VSS bit8 VDD toDAC8 clk8) sar_mux
I85 (VDD VSS bit7 VDD toDAC7 clk7) sar_mux
I89 (VDD VSS bit6 VDD toDAC6 clk6) sar_mux
I101 (VDD VSS bit3 VDD toDAC3 clk3) sar_mux
I109 (VDD VSS bit1 VDD toDAC1 clk1) sar_mux
I56 (VDD VSS VSS VDD net0371 compOut) sar_mux
I46 (VDD VSS VSS VDD net0310 compOut) sar_mux
I97 (VDD VSS bit4 VDD toDAC4 clk4) sar_mux
I113 (VDD VSS bit0 VDD toDAC0 clk0) sar_mux
I105 (VDD VSS bit2 VDD toDAC2 clk2) sar_mux
I76 (VDD VSS bit9 VDD toDAC9 clk9) sar_mux
I51 (VDD VSS VSS VDD net0377 compOut) sar_mux
I41 (VDD VSS VSS VDD net180 compOut) sar_mux
I36 (VDD VSS VSS VDD net186 compOut) sar_mux
I31 (VDD VSS VSS VDD net192 compOut) sar_mux
I21 (VDD VSS VSS VDD net204 compOut) sar_mux
I16 (VDD VSS VSS VDD net210 compOut) sar_mux
I11 (VDD VSS VSS VDD net216 compOut) sar_mux
I93 (VDD VSS bit5 VDD toDAC5 clk5) sar_mux
I26 (VDD VSS VSS VDD net198 compOut) sar_mux
